9/23/2023 0 Comments Period counter vhdl![]() ![]() ![]() ![]() There isn’t a chance in hell of the Spartan 6 on his Papilio Pro board ever being able to measure that, but he is able to measure a 500 MHz clock, something that would be impossible without his clever bit of code. used a 5-bit Gray code, getting rid of the problem of the ‘11111’ to ‘00000’ rollover of a normal binary counter.īecause is using a 5 bit clock with 31 edges sampled at 32 MHz, he can theoretically sample a 992 MHz clock. The solution is to have the input signal drive a very small counter – only five bits – and sample the counter using a slower clock on board the FPGA. Also, any sampling would have to run at least twice as fast as the input signal – not a great idea if you’re counting really fast clocks. This is a terrible idea: long counters have a lot of propagation delays. The simplest solution for counting a clock would be to count a clock for a second with a huge, 30-bit counter. Being a bit more clever turns the task into a cakewalk, with a low-end FPGA being able to count clocks over 500 MHz. As it turns out, it’s pretty hard with a naive solution. He wondered if he could do the same on an FPGA, and how hard it would be to count high clock rates. During one of ’s many forum lurking sessions, he came across a discussion about frequency counting on a CPLD. ![]()
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |